1. Field of the Invention
This invention relates to integrated circuits and more particularly to buried contact modules that form contact junctions within integrated circuits.
2. Description of the Relevant Art
Buried contact modules for forming contact junctions are well-known in integrated circuit technology. A conventional process for fabricating a buried contact module involves the use of polysilicon to directly contact a diffusion region of an N-type or a P-type well that is formed on, for example, a silicon substrate.
Several problems are associated with contact junctions formed with buried contact modules. In general, it is desirable to fabricate a contact junction having a low resistivity. Low polysilicon resistivity is particularly desirable for high speed applications. To achieve this low contact resistivity, the polysilicon portion of the buried contact module is heavily doped with either an N-type or a P-type material. However, such a high dopant concentration in the polysilicon region can result in an unacceptably deep junction depth. As a result, a phenomenon known as device punch-through occurs, as explained in more detail below.
The problems associated with buried contact modules will be better understood with reference to FIG. 1. FIG. 1 illustrates a pair of contact junctions formed by two separate buried contact modules. A first buried contact module is fabricated with a polysilicon region 10 and a P-type well region 12. A second buried contact module is fabricated with another polysilicon region 14 and the P-type well region 12. A field oxide region 16 provides isolation between the contact junctions formed by the two buried contact modules. Polysilicon regions 10 and 14 are connected to separate metal conductors 18 and 20, respectively, that connect to, for example, external pins of the integrated circuit. The buried contact modules illustrated in FIG. 1 are shown in combination with an N-type substrate region 22 on which the P-type well region 12 is formed. FIG. 1 also illustrates a pair of gate dielectric regions 24 and 25 and a pair of gate regions 26 and 27.
Each of the polysilicon regions 10 and 14 are heavily doped by phosphorous ion implantation or doped by POCl.sub.3 source. The polysilicon regions 10 and 14 thus have an N-type conductivity. As a result of this N+ type dopant, phosphorous ions diffuse into the P-type well region 12 from each polysilicon region 10 and 14 and thereby form active areas which allow electrical conduction to, for example, a source or a drain region (not shown) formed in the P-type well region 12. The higher the concentration of phosphorous implantation in the polysilicon regions 10 and 14, the deeper the active area defined by the diffused phosphorous ions in the P-type well region 12. The depth of the phosphorous diffusion into the well region 12 is known as the buried contact junction depth X.sub.j. As shown in FIG. 1, X.sub.j1 illustrates the junction depth of the buried contact modules wherein a relatively low concentration of dopant is provided in the polysilicon regions 10 and 14, while X.sub.j2 illustrates the junction depths wherein a relatively high concentration of dopant is provided in the polysilicon region 10 and 14.
As illustrated by the merging arrows a and b of FIG. 1, when the dopant concentration of the polysilicon regions 10 and 14 is increased, the active areas of the respective buried contact modules become closer together. If the active areas become too close, the field oxide region 16 does not provide isolation between the contact junctions when a voltage differential is applied between terminals V1 and V2. When this occurs, the punch-through phenomenon occurs wherein current is allowed to flow between the active areas of the buried contact junctions.
Therefore, to avoid the punch-through phenomenon, the integrated circuit must be operated under limited conditions to assure that the voltage differential between contact junctions does not reach the breakdown level. Furthermore, compromises must be made by the designer of the device in consideration of interconnect polysilicon resistance, contact resistance, punch-through voltage and junction leakage current.